1. Field
The present invention relates to an embedded system that stores configuration data used for a logic circuit device such as FPGA (Field Programmable Gate Array) and PLD (Programmable Logic Device) having an internal circuit that is programmable in an external storage, and incorporates the configuration data stored in the external storage into the logic circuit and a control method therefore.
Particularly, the present invention relates to an embedded system that minimizes a down time by appropriately avoiding problems caused by hardware/software errors occurring in an FPGA or the like and a control method therefore.
2. Description of the Related Art
In recent years, embedded systems having firmware that can be updated from a remote location have been widely used.
Here, the firmware is software incorporated in an equipment to perform basic control of firmware/hardware and includes, for example, a real-time operating system (OS).
FIG. 7 is a schematic diagram for illustrating a firmware update system having a typical embedded system.
The firmware update system in FIG. 7 comprises an embedded system 50, a service processor 60, and a maintenance center server 70. The embedded system 50 is connected to the service processor 60 via a network (not shown) and the service processor 60 is connected to the maintenance center server 70 via a network.
Here, the maintenance center server 70 is a device that outputs to the service processor 60 firmware whose source of causing a hardware/software error has been fixed (hereinafter called fixed firmware) periodically or after the hardware/software error occurs in the embedded system 50.
The service processor 60 is a device that monitors a hardware/software error of the embedded system 50 and, when an error occurs in the embedded system 50, automatically notifies the maintenance center server 70 of the error.
Then, when a fixed firmware is acquired from the maintenance center server 70, the service processor 60 stores the fixed firmware in a storage device 61 to enable application of the fixed firmware to the embedded system 50. The storage device 61 is a storage device for storing fixed firmware and the like.
The embedded system 50 is a system that performs various kinds of processing using the fixed firmware applied by the service processor 60.
The configuration of the embedded system 50 will be described using FIG. 7. The embedded system 50 is constructed by connecting a flash memory 51, a microprocessor 52, FPGA 53, a configuration ROM (C-ROM) 54, a main memory 55, and a network interface 56 using a bus 57.
The flash memory 51 is a kind of a non-volatile memory whose data can be rewritten and has a boot up program area, a control area, a first program area, and a second program area.
The boot up program area is an area where a boot up program is stored in the flash memory 51 and the control area is an area where various kinds of control information of programs stored in the first program area and the second program area are stored in the flash memory 51.
The first program area and the second program area are areas where various kinds of programs (programs corresponding to the above-discussed fixed firmware) are stored.
A program stored in the first program area will be denoted as a “first program” and a program stored in the second program area will be denoted as a “second program” below.
Here, the data structure of the control area will be described. FIG. 8 is a diagram illustrating a data structure of the control area. As shown in FIG. 8, the control area has a plurality of areas ranging from the first generation to the n-th generation (n is an integer equal to 2 or greater) and each control area has a valid/invalid flag, an operating version number, program area information, switching factors, and switching dates/times.
The valid/invalid flag is a flag indicating whether or not information in the corresponding control area is valid. If, for example, the valid/invalid flag of the control area (first generation) is valid, information stored in the control area (first generation) is “valid.” The valid/invalid flag of a control area storing old control information is set to “invalid.”
The operating version number shows information of a program version number of a program stored in the first program area or second program area. The program area information is information of a boot-up area of a control program, that is, information showing which of the first program and the second program to boot up.
The switching factors are factors when programs were switched, that is, information regarding which factor caused programs to switch, and the switching dates/times are information regarding dates/times when programs were switched.
Returning to the description of FIG. 7, the microprocessor 52 is a means for controlling the embedded system 50 by a first program or a second program read by the main memory 55 from the flash memory 51.
Based on program area information (See FIG. 8) of the flash memory 51, the microprocessor 52 selects the first program or the second program and uses the selected program to control the embedded system 50.
Moreover, the microprocessor 52 refers to the flash memory 51 when updating firmware (when fixed firmware is received from the service processor) and searches for control information (information stored in the control area) for which a valid flag is set.
Then, based on program area information of the control information, an area into which an update program should be written is determined.
If, for example, the first program area is an area of the current system (where the first program is used for various control operations) and the second program area is an area of the backup system (the second program is not used), the microprocessor 52 writes the update program into the second program area.
Then, the written update program is used by a firmware reset (self reset) in which a reset routine is executed by the firmware for rebooting.
The FPGA 53 is a means for controlling the main memory 55, the flash memory 51 and the like in accordance with a control signal from the microprocessor 52 and is a programmable logic circuit such as a FPGA and a programmable logic device (PLD). The C-ROM 54 is a means for storing programs used by the FPGA 53.
The main memory 55 is a means for storing various kinds of information and comprises SDRAM (Synchronous Dynamic Random Access Memory) or normal DRAM (Dynamic Random Access Memory). The network interface 56 is a means for communicating mainly with the service processor 60 using a predetermined communication protocol.
As described above, the typical embedded system 50 is started up by selecting an optimal control program from a plurality of control programs (such as the first program and second program) stored in the flash memory 51 and also writes an update program, which is a fixed firmware, into a program area to be a backup system to update the firmware.
Therefore, while it becomes possible to relatively reduce the time required to solve a problem and reduce the number of operation processes to apply fixed firmware, there exists a problem because the aforementioned embedded system 50 can update only control programs and cannot update configuration data of the FPGA 53 stored in the C-ROM 54.
Thus, when an error occurs in a logic circuit of the FPGA or a boot up program, hardware of the embedded system 50 must directly be replaced, thereby causing problems including requiring a longer time for troubleshooting.